Development #48
AMBPEX5_SX50T_WISHBONE
| Status: | Confirmed | Start date: | 05/12/2013 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | 07/01/2013 | |
| Assignee: | Dmitry Smekhov | % Done: | 100% |
|
| Category: | - | Spent time: | 7.00 hours | |
| Target version: | - |
Description
PCI Express controller for WISHBONE bus;
Virtex5 SX50T
PCI Express v1.1 x8
Subtasks
History
Updated by Dmitry Smekhov almost 9 years ago
Simulation is ok. Revision r17
Updated by Dmitry Smekhov over 8 years ago
Correct core64_pb_disp; Add signals timeout_cnt, slave_timeout
Updated by Dmitry Smekhov over 8 years ago
Add register in the TEST_GEN block:
0x10 - STATUS
0x11 - BLOCK_WR
0x12 - sig 0xAAAAAAAAA - is temporary word
wb_test read data from TEST_GEN with errors.
Revision: r30
Updated by Dmitry Smekhov over 8 years ago
I set 125 MHz to clk for WISHBONE bus.
Data transfered from TEST_GEN to computer without error.
Revision r32