Struct

Version 1 (Dmitry Smekhov, 02/25/2012 12:17 am)

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h1. Struct
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The basis of the controller is a component of [[pcie_core64_m1]]
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It combines IP Core Xilinx, core logic for generation and reception of packets, access to the registers and the DMA controller.
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Block diagram:
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!pcie_core64_m1_en.png!
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The component has two buses:
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* Bus [[BAR0 Bus]] - to access the registers BAR0
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* Bus [[PLD Bus]] - for single and block calls to the BAR1
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DMA channel only works with the bus PLD Bus.
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In the space BAR0 implemented control registers. They are grouped into blocks of management. To control the DMA channels control blocks allocated 4.5;
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Access to the control unit 0-3 is performed through the bus [[BAR0 Bus]].
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Component [[pcie_core64_m2]] is an example of a controller in the system. It adds a control unit generates the MAIN and local bus [[LC Bus]]
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!pcie_core64_m2_en.png!
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Component [[pcie_core64_wishbone]] as an example of a controller in the system. It adds a control unit generates the MAIN and local bus [[WISHBONE]]
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!pcie_core64_wishbone_en.png!
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Components  pcie_core64_m1 and pcie_core64_m2 designed for Virtex 5
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Their analogs for Virtex 6  is pcie_core64_m4  and pcie_core64_m5.
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Their analogs for Virtex 6  is pcie_core64_m6  and pcie_core64_m7.