Struct¶

The basis of the controller is a component of pcie_core64_m1
It combines IP Core Xilinx, core logic for generation and reception of packets, access to the registers and the DMA controller.
Block diagram:

The component has two buses:

• Bus BAR0 Bus - to access the registers BAR0
• Bus PLD Bus - for single and block calls to the BAR1

DMA channel only works with the bus PLD Bus.
In the space BAR0 implemented control registers. They are grouped into blocks of management. To control the DMA channels control blocks allocated 4.5;
Access to the control unit 0-3 is performed through the bus BAR0 Bus.

Component pcie_core64_m2 is an example of a controller in the system. It adds a control unit generates the MAIN and local bus LC Bus

Component pcie_core64_wishbone as an example of a controller in the system. It adds a control unit generates the MAIN and local bus WISHBONE

Components pcie_core64_m1 and pcie_core64_m2 designed for Virtex 5

Their analogs for Virtex 6 is pcie_core64_m4 and pcie_core64_m5.
Their analogs for Virtex 6 is pcie_core64_m6 and pcie_core64_m7.