FAQ¶

Global¶

Is it work ?¶

Yes.

What is licensing ?¶

LGPL.

I see an error on the site, text, description.¶

I do not know much English, correct me please.

Why do you need this?¶

1. I want to keep the knowledge of this controller
2. I want to test on different hardware.

And now you have all of the projects will be OpenSource?¶

No.

A project on which modules are already working?¶

• Virtex 5 - AMBPEX5, ADP201x1, FMC105P
• Virtex 6 - FMC114V, ML605
• Spartan 6 - FMC103E, SP605

Please let me know if you do a project for the new modules.

FPGA¶

Why such strange names : pcie_core64_m1, pcie_core64_m2, etc ?¶

• pcie_core - PCI Express controller
• 64 - it is local bus of 64 bits
• m1, m2, ... - it is label for different bus and FPGA

What is the difference bettwen pcie_core64_m1 and pcie_core64_m2 ?¶

• pcie_core64_m1 is a PCI Express controller for Virtex 5 and PLD_Bus. It have only base function. It have only PE_EXT_FIFO blocks.
• pcie_core64_m2 include pcie_core64_m1. It have LC_Bus and PE_MAIN block.

Why PLD_Bus ?¶

PLD_Bus that needed to separate the implementation of the controller on the type of bus. PLD_Bus can be adapted to the parallel or serial buses. At the moment, there are components for connection to the LC_Bus and WISHBONE.

Is it possible to connect to PLD_Bus AXI?¶

Probably.

Why is it necessary for the separation of space and BAR0 BAR1?¶

To separate control channel DMA and the application.
Differences:

• In the space BAR0 imposed limitation - it must be implemented PE_EXT_FIFO blocks to control the channel DMA.
• In the space BAR1 no restrictions are imposed.
• BAR0 - always operates at the frequency components of IP Core Xilinx. (250 MHz for Virtex 5)
• BAR1 - can operate at a different frequency (eg 266 MHz)
• DMA channel only works with BAR1
• BAR0 - fixed type bus
• BAR1 - Bus PLD_Bus with the possibility of switching to LC_Bus, WISHBONE.