History

FAQ

Global

Does it work ?

Yes.

What type of licensing for this project?

LGPL.

What should I do when I'he found an error on this website ?

My English is not good, correct me please.

Why do you need this?

  1. I want to keep the knowledge of this controller
  2. I want to test it on different hardware.

All of your projects will be OpenSource, won't they ?

No.

Which devices can work with this project ?

  • Virtex 5 - AMBPEX5, ADP201x1, FMC105P
  • Virtex 6 - FMC114V, ML605
  • Spartan 6 - FMC103E, SP605

Please let me know if you made a project for the new modules.

FPGA

Why do you use these strange names: pcie_core64_m1, pcie_core64_m2, etc ?

  • pcie_core - PCI Express controller
  • 64 - it is local bus of 64 bits
  • m1, m2, ... - it is label for different bus and FPGA

What is the difference between pcie_core64_m1 and pcie_core64_m2 ?

  • pcie_core64_m1 is a PCI Express controller for Virtex 5 and PLD_Bus. It has only base function. It have only PE_EXT_FIFO blocks.
  • pcie_core64_m2 include pcie_core64_m1. It has LC_Bus and PE_MAIN block.

Why do you need PLD_Bus ?

PLD_Bus is used needed to separate the implementation of the controller on the type of bus. PLD_Bus can be set up to the parallel or serial buses. There are components for connection to the LC_Bus and WISHBONE at the moment.

Is it possible to connect to AXI via PLD_Bus ?

Probably.

Why is it necessary to separate on BAR0 and BAR1 resources ?

To separate control channel DMA and the application.
Differences:
  • The BAR0 resources have a restriction - PE_EXT_FIFO blocks must be implemented to control the channel DMA
  • The BAR1 resources have no restrictions
  • BAR0 - always operates on the frequency of Xilinx IP Core components. (250 MHz for Virtex 5)
  • BAR1 - can operate at a different frequency (eg 266 MHz)
  • DMA channel works only with BAR1
  • BAR0 - has fixed bus type
  • BAR1 - has PLD_Bus with the possibility of switching to LC_Bus or to WISHBONE.

Is it necessarily to use 32-bit instructions to get an access to registers ?

Required. Byte operations are not supported.

And what happens if I give the command to read or write bytes?

I do not know. Just try it and let me know about the result.

I absolutely have to use a byte operation. What to do?

You should modify some components of the project such as core64_rx_engine, core64_tx_engine, core64_reg_access, core64_pb_disp, core64_pb_transaction; But it will be another controller.

DMA channel produces a transmission unit in 4096 bytes in a single operation. Should I use it too?

Yes. This is the fundamental property. 4096 bytes is the page size for Intel x86 computers. The restriction on the multiplicity of 4096 bytes for the size and the start address of the data controller has significantly simplified.

I absolutely want to use another DMA buffer size which differs from 4096 bytes. What should I do?

Just make another controller.