FAQ en
Version 1 (Dmitry Smekhov, 04/20/2013 11:36 pm) → Version 2/3 (Dmitry Smekhov, 04/20/2013 11:41 pm)
h1. FAQ
h2. Global
h3. Is it work ?
Yes.
h3. What is licensing ?
LGPL.
h3. I see an error on the site, text, description.
I do not know much English, correct me please.
h3. Why do you need this?
# I want to keep the knowledge of this controller
# I want to test on different hardware.
h3. And now you have all of the projects will be OpenSource?
No.
h3. A project on which modules are already working?
* Virtex 5 - AMBPEX5, ADP201x1, FMC105P
* Virtex 6 - FMC114V, ML605
* Spartan 6 - FMC103E, SP605
Please let me know if you do a project for the new modules.
h2. FPGA
h3. Why such strange names : pcie_core64_m1, pcie_core64_m2, etc ?
* pcie_core - PCI Express controller
* 64 - it is local bus of 64 bits
* m1, m2, ... - it is label for different bus and FPGA
h3. What is the difference bettwen pcie_core64_m1 and pcie_core64_m2 ?
* pcie_core64_m1 is a PCI Express controller for Virtex 5 and PLD_Bus. It have only base function. It have only PE_EXT_FIFO blocks.
* pcie_core64_m2 include pcie_core64_m1. It have LC_Bus and PE_MAIN block.
h3. Why PLD_Bus ?
PLD_Bus that needed to separate the implementation of the controller on the type of bus. PLD_Bus can be adapted to the parallel or serial buses. At the moment, there are components for connection to the LC_Bus and WISHBONE.
h3. Is it possible to connect to PLD_Bus AXI?
Probably.
h3. Why is it necessary for the separation of space and BAR0 BAR1?
To separate control channel DMA and the application.
Differences:
* In the space BAR0 imposed limitation - it must be implemented PE_EXT_FIFO blocks to control the channel DMA.
* In the space BAR1 no restrictions are imposed.
* BAR0 - always operates at the frequency components of IP Core Xilinx. (250 MHz for Virtex 5)
* BAR1 - can operate at a different frequency (eg 266 MHz)
* DMA channel only works with BAR1
* BAR0 - fixed type bus
* BAR1 - Bus PLD_Bus with the possibility of switching to LC_Bus, WISHBONE.
h3. Do I have to do to access registers via a 32-bit instructions?
Required. Byte operations are not supported.
h3. And what happens if I give the command to read or write bytes?
I do not know. Try it out and let me know about the result.
h3. I absolutely have to use a byte operation. What to do?
Need to modify the components of core64_rx_engine, core64_tx_engine, core64_reg_access, core64_pb_disp, core64_pb_transaction; But it is another controller.
h3. DMA channel in a single operation produces a transmission unit in 4096. I have to?
Yes. This fundamental property. 4096 is the page size for computers Intel x86. The restriction on the multiplicity of 4096 bytes for the size and the start address of the data controller has significantly simplified.
h3. I absolutely have to use the channel DMA buffer size is not a multiple of 4096 bytes. What to do?
Make another controller.