FAQ en
Version 3 (Dmitry Smekhov, 06/06/2013 12:11 am)
| 1 | 1 | h1. FAQ |
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| 2 | 1 | ||
| 3 | 1 | h2. Global |
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| 4 | 1 | ||
| 5 | 3 | Dmitry Smekhov | h3. Does it work ? |
| 6 | 1 | ||
| 7 | 1 | Yes. |
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| 8 | 1 | ||
| 9 | 3 | Dmitry Smekhov | h3. What type of licensing for this project? |
| 10 | 1 | ||
| 11 | 1 | LGPL. |
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| 12 | 1 | ||
| 13 | 3 | Dmitry Smekhov | h3. What should I do when I'he found an error on this website ? |
| 14 | 1 | ||
| 15 | 3 | Dmitry Smekhov | My English is not good, correct me please. |
| 16 | 1 | ||
| 17 | 1 | h3. Why do you need this? |
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| 18 | 1 | ||
| 19 | 1 | # I want to keep the knowledge of this controller |
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| 20 | 3 | Dmitry Smekhov | # I want to test it on different hardware. |
| 21 | 1 | ||
| 22 | 3 | Dmitry Smekhov | h3. All of your projects will be OpenSource, won't they ? |
| 23 | 1 | ||
| 24 | 1 | No. |
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| 25 | 1 | ||
| 26 | 3 | Dmitry Smekhov | h3. Which devices can work with this project ? |
| 27 | 1 | ||
| 28 | 1 | * Virtex 5 - AMBPEX5, ADP201x1, FMC105P |
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| 29 | 1 | * Virtex 6 - FMC114V, ML605 |
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| 30 | 1 | * Spartan 6 - FMC103E, SP605 |
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| 31 | 1 | ||
| 32 | 3 | Dmitry Smekhov | Please let me know if you made a project for the new modules. |
| 33 | 1 | ||
| 34 | 1 | h2. FPGA |
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| 35 | 1 | ||
| 36 | 3 | Dmitry Smekhov | h3. Why do you use these strange names: pcie_core64_m1, pcie_core64_m2, etc ? |
| 37 | 1 | ||
| 38 | 1 | * pcie_core - PCI Express controller |
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| 39 | 1 | * 64 - it is local bus of 64 bits |
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| 40 | 1 | * m1, m2, ... - it is label for different bus and FPGA |
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| 41 | 1 | ||
| 42 | 3 | Dmitry Smekhov | h3. What is the difference between pcie_core64_m1 and pcie_core64_m2 ? |
| 43 | 1 | ||
| 44 | 3 | Dmitry Smekhov | * pcie_core64_m1 is a PCI Express controller for Virtex 5 and PLD_Bus. It has only base function. It have only PE_EXT_FIFO blocks. |
| 45 | 3 | Dmitry Smekhov | * pcie_core64_m2 include pcie_core64_m1. It has LC_Bus and PE_MAIN block. |
| 46 | 1 | ||
| 47 | 3 | Dmitry Smekhov | h3. Why do you need PLD_Bus ? |
| 48 | 1 | ||
| 49 | 3 | Dmitry Smekhov | PLD_Bus is used needed to separate the implementation of the controller on the type of bus. PLD_Bus can be set up to the parallel or serial buses. There are components for connection to the LC_Bus and WISHBONE at the moment. |
| 50 | 1 | ||
| 51 | 3 | Dmitry Smekhov | h3. Is it possible to connect to AXI via PLD_Bus ? |
| 52 | 1 | ||
| 53 | 1 | Probably. |
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| 54 | 1 | ||
| 55 | 3 | Dmitry Smekhov | h3. Why is it necessary to separate on BAR0 and BAR1 resources ? |
| 56 | 1 | ||
| 57 | 1 | To separate control channel DMA and the application. |
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| 58 | 1 | Differences: |
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| 59 | 3 | Dmitry Smekhov | * The BAR0 resources have a restriction - PE_EXT_FIFO blocks must be implemented to control the channel DMA |
| 60 | 3 | Dmitry Smekhov | * The BAR1 resources have no restrictions |
| 61 | 3 | Dmitry Smekhov | * BAR0 - always operates on the frequency of Xilinx IP Core components. (250 MHz for Virtex 5) |
| 62 | 1 | * BAR1 - can operate at a different frequency (eg 266 MHz) |
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| 63 | 3 | Dmitry Smekhov | * DMA channel works only with BAR1 |
| 64 | 3 | Dmitry Smekhov | * BAR0 - has fixed bus type |
| 65 | 3 | Dmitry Smekhov | * BAR1 - has PLD_Bus with the possibility of switching to LC_Bus or to WISHBONE. |
| 66 | 2 | Dmitry Smekhov | |
| 67 | 2 | Dmitry Smekhov | |
| 68 | 3 | Dmitry Smekhov | h3. Is it necessarily to use 32-bit instructions to get an access to registers ? |
| 69 | 2 | Dmitry Smekhov | |
| 70 | 2 | Dmitry Smekhov | Required. Byte operations are not supported. |
| 71 | 2 | Dmitry Smekhov | |
| 72 | 2 | Dmitry Smekhov | h3. And what happens if I give the command to read or write bytes? |
| 73 | 2 | Dmitry Smekhov | |
| 74 | 3 | Dmitry Smekhov | I do not know. Just try it and let me know about the result. |
| 75 | 2 | Dmitry Smekhov | |
| 76 | 2 | Dmitry Smekhov | h3. I absolutely have to use a byte operation. What to do? |
| 77 | 2 | Dmitry Smekhov | |
| 78 | 3 | Dmitry Smekhov | You should modify some components of the project such as core64_rx_engine, core64_tx_engine, core64_reg_access, core64_pb_disp, core64_pb_transaction; But it will be another controller. |
| 79 | 2 | Dmitry Smekhov | |
| 80 | 3 | Dmitry Smekhov | h3. DMA channel produces a transmission unit in 4096 bytes in a single operation. Should I use it too? |
| 81 | 2 | Dmitry Smekhov | |
| 82 | 3 | Dmitry Smekhov | Yes. This is the fundamental property. 4096 bytes is the page size for Intel x86 computers. The restriction on the multiplicity of 4096 bytes for the size and the start address of the data controller has significantly simplified. |
| 83 | 2 | Dmitry Smekhov | |
| 84 | 3 | Dmitry Smekhov | h3. I absolutely want to use another DMA buffer size which differs from 4096 bytes. What should I do? |
| 85 | 2 | Dmitry Smekhov | |
| 86 | 3 | Dmitry Smekhov | Just make another controller. |