FAQ en
Version 1 (Dmitry Smekhov, 04/20/2013 11:36 pm)
| 1 | 1 | h1. FAQ |
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| 2 | 1 | ||
| 3 | 1 | h2. Global |
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| 4 | 1 | ||
| 5 | 1 | h3. Is it work ? |
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| 6 | 1 | ||
| 7 | 1 | Yes. |
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| 8 | 1 | ||
| 9 | 1 | h3. What is licensing ? |
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| 10 | 1 | ||
| 11 | 1 | LGPL. |
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| 12 | 1 | ||
| 13 | 1 | h3. I see an error on the site, text, description. |
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| 14 | 1 | ||
| 15 | 1 | I do not know much English, correct me please. |
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| 16 | 1 | ||
| 17 | 1 | h3. Why do you need this? |
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| 18 | 1 | ||
| 19 | 1 | # I want to keep the knowledge of this controller |
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| 20 | 1 | # I want to test on different hardware. |
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| 21 | 1 | ||
| 22 | 1 | h3. And now you have all of the projects will be OpenSource? |
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| 23 | 1 | ||
| 24 | 1 | No. |
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| 25 | 1 | ||
| 26 | 1 | h3. A project on which modules are already working? |
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| 27 | 1 | ||
| 28 | 1 | * Virtex 5 - AMBPEX5, ADP201x1, FMC105P |
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| 29 | 1 | * Virtex 6 - FMC114V, ML605 |
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| 30 | 1 | * Spartan 6 - FMC103E, SP605 |
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| 31 | 1 | ||
| 32 | 1 | Please let me know if you do a project for the new modules. |
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| 33 | 1 | ||
| 34 | 1 | h2. FPGA |
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| 35 | 1 | ||
| 36 | 1 | h3. Why such strange names : pcie_core64_m1, pcie_core64_m2, etc ? |
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| 37 | 1 | ||
| 38 | 1 | * pcie_core - PCI Express controller |
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| 39 | 1 | * 64 - it is local bus of 64 bits |
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| 40 | 1 | * m1, m2, ... - it is label for different bus and FPGA |
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| 41 | 1 | ||
| 42 | 1 | h3. What is the difference bettwen pcie_core64_m1 and pcie_core64_m2 ? |
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| 43 | 1 | ||
| 44 | 1 | * pcie_core64_m1 is a PCI Express controller for Virtex 5 and PLD_Bus. It have only base function. It have only PE_EXT_FIFO blocks. |
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| 45 | 1 | * pcie_core64_m2 include pcie_core64_m1. It have LC_Bus and PE_MAIN block. |
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| 46 | 1 | ||
| 47 | 1 | h3. Why PLD_Bus ? |
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| 48 | 1 | ||
| 49 | 1 | PLD_Bus that needed to separate the implementation of the controller on the type of bus. PLD_Bus can be adapted to the parallel or serial buses. At the moment, there are components for connection to the LC_Bus and WISHBONE. |
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| 50 | 1 | ||
| 51 | 1 | h3. Is it possible to connect to PLD_Bus AXI? |
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| 52 | 1 | ||
| 53 | 1 | Probably. |
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| 54 | 1 | ||
| 55 | 1 | h3. Why is it necessary for the separation of space and BAR0 BAR1? |
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| 56 | 1 | ||
| 57 | 1 | To separate control channel DMA and the application. |
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| 58 | 1 | Differences: |
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| 59 | 1 | * In the space BAR0 imposed limitation - it must be implemented PE_EXT_FIFO blocks to control the channel DMA. |
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| 60 | 1 | * In the space BAR1 no restrictions are imposed. |
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| 61 | 1 | * BAR0 - always operates at the frequency components of IP Core Xilinx. (250 MHz for Virtex 5) |
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| 62 | 1 | * BAR1 - can operate at a different frequency (eg 266 MHz) |
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| 63 | 1 | * DMA channel only works with BAR1 |
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| 64 | 1 | * BAR0 - fixed type bus |
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| 65 | 1 | * BAR1 - Bus PLD_Bus with the possibility of switching to LC_Bus, WISHBONE. |