PCIe Modelsim

Added by ravi kumar over 1 year ago

Hello Sir,

I am using Virtex-5 device to test it for PCIe configuration. Do you have any documentation of Modelsim simulations?. I would like to have some preliminary screenshots of the Modelsim results so as to ensure that my tool are in place and are working alright.

Regards,
Ravi


Replies (3)

RE: PCIe Modelsim - Added by Dmitry Smekhov over 1 year ago

Hello,
Unfortunately, I do not work with Modelsim. I prefer an Active-HDL.

My project can be simulated is ModelSim;
See: http://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk/projects/ambpex5_v20_sx50t_core/src/testbench/modelsim

Regards

RE: PCIe Modelsim - Added by ravi kumar over 1 year ago

Hello Sir,

Thankyou very much for your kind e-mail reply. Here, I am attaching the screenshot of the simulations results and Transcript file. Could you please confirm if the simulation results are as expected?. With this I can confirm that I do not have any compatibility issues with the modelsim 10.2C version.

Btw, could you provide me any documentation/notes about this project?.

Thanks and Regards,
Ravi

Transcript (122.3 kB)

screenshot_pcie.png (76.1 kB)

RE: PCIe Modelsim - Added by Dmitry Smekhov over 1 year ago

It is right simulation;

Failure: End of TEST; Ending simulation (not a Failure) - it is break for simulation. It is normal;

There are more information about test in the file "test.log"
Please, see file "test.log"

File is created in process pr_main in the stend_ambpex5_core_m2.vhd


pr_main: process 

variable    data    : std_logic_vector( 31 downto 0 );
variable     str     : LINE;        -- pointer to string
begin

    --test_init( "src\log\test.log" );
    test_init( "test.log" );

    wait for 180 us;    

    --test_dsc_incorrect( cmd, ret );       

    --test_read_4kb( cmd, ret );
    --test_adm_read_8kb( cmd, ret );
    test_adm_read_16kb( cmd, ret );
    --test_adm_write_16kb( cmd, ret );
    --test_block_main( cmd, ret );

    test_close;
        --
        -- Print Final Banner
        report "Init END OF TEST" severity WARNING;
        assert false
        report "End of TEST; Ending simulation (not a Failure)" 
        severity FAILURE;
    wait;

end process;

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