DS_DMA

h1. WB TEST 

The program is designed to test the operation of the module with the FPGA project WISHBONE.

h2. Features

* Display information BAR0 - list of control units

* Display information BAR1 - list of control units TEST_CHECK, TEST_GENERATE

* Checking of the data input from the TEST_GENERATE

* Checking of the data output to the TEST_CHECK

* Synchronous data input from the TEST_GENERATE and data output to the TEST_CHECK

* The calculation of the current exchange rate - in the interval 4 seconds

* Calculating the average exchange rate - with the launch of

* Error logging

h2. Source code

The source code of the program is in the repository: *trunk/soft/linux/application/wb_test*

Catalogs:

* *bin* - executable and configuration files

* *src* - source code

Catalog *src*

* *Makefile* - for build 

* *work* - source code

The program uses the files in the directory *trunk/soft/linux/common/*

*  *pex* -  contains class files: *pex_board*

*  *utils* - contains useful files

h2. Starting the program

Before starting the program you want to load driver *pexdrv*.

To load the driver script is used *insert* from the directory *soft/linux/driver*

Loading the driver: *sudo ./Insert*.

Unloading Driver: *sudo rmmod pexdrv*

To view a list of available devices can run the command *ls /dev/AMB* *

The device name is formed as follows: /dev/<device name> <sequencenumber of the device>

For example: /dev/AMBPEX50

Launch:

 *./wb_test  <device name> <configuration file> [<configuration file>]*

* <device name> - logical device name, for example */dev/pexdrv0* (not currently implemented, is always used *pexdrv0*)

* <configuration file> - cfg file with parameters

List of configuration files:

* *test_gen.cfg* - inputs from the TEST_GENERATE

* *out_check.cfg* - output to the TEST_CHECK

If given two file that runs two of the testing process, if only one file is only one testing process.

h2. Example: 

Command: *./wb_test test_gen.cfg*

Output:

<pre>

dsmv@dsmv-linux:~/pcie_ds_dma/trunk/soft/linux/application/wb_test/bin$ ./wb_test test_gen.cfg

Map BAR0: 0xfe800000 -> 0x7f4b4ff03000

Map BAR1: 0xfe600000 -> 0x7f4b4fd03000

core_init()

core_init(): BlockID = 0x1013, BlockVER = 0x101.

core_init(): DeviceID = 0x5504, DeviceRev = 0x210.

core_init(): PldVER = 0x104.

core_init(): Block count = 8.

core_init(): Channel(ID) = 0(0x18), FIFO size = 4096 Bytes, DMA Dir = 3, Max DMA size = 1024 MBytes, resource = 0x2.

core_init(): Channel(ID) = 1(0x18), FIFO size = 4096 Bytes, DMA Dir = 3, Max DMA size = 1024 MBytes, resource = 0x2.

core_init(): Prepare ADM PLD.

Board PEXDRV open succesfully

FPGA WB

WB block info:

 0  0x001A TEST_CHECK      MOD: 0  VER: 1.0 

 1  0x001B TEST_GENERATE   MOD: 0  VER: 1.0 

Read parameters from file: test_gen.cfg

Parameters:

CntBuffer  8

CntBlockInBuffer  1

SizeBlockOfWords  262144

isCycle  1

isSystem  1

isAgreeMode  1

strmNo  1

isTest  2

FifoRdy  1

Cnt1  0

Cnt2  0

DataType  6

DataFix  1

Allocation memory: 

 Type of buffer:    system memory

 Buffer size: 8 MB  (8x1 MB)

0: 0x8f400000 -> 0x7f4b513ef000

1: 0x8f500000 -> 0x7f4b4fc03000

2: 0x8f600000 -> 0x7f4b4fb03000

3: 0x8f700000 -> 0x7f4b4fa03000

4: 0x89800000 -> 0x7f4b4f903000

5: 0x89900000 -> 0x7f4b4f803000

6: 0x89a00000 -> 0x7f4b4f703000

7: 0x89b00000 -> 0x7f4b4f603000

Stub: 0xb5bcd000 -> 0x7f4b5150a000

Allocate stream memory - Ok

core_set_local_addr(): DmaChan=1 addr=0x00003000 

Stream working in adjust mode

core_start_dma(): DmaChan=1 IsCycling=1 

core_start_dma(): IOCTL_AMB_START_MEMIO   core_start_dma - OK 

ID=0x001B 

VER=0x0100 

GEN_CTRL=0x0001 

GEN_CTRL=0x06A0 

             BLOCK_WR   BLOCK_RD   BLOCK_OK  BLOCK_ERR   SPD_CURR    SPD_AVR     STATUS  SIG         TIME  

 TRD :   0     245366     245366     245366          0      799.8      799.8     0x0309  0xAAAAAAAA  5:06 

</pre>

There is parameters in the last line.

* *BLOCK_WR* - number of the transmitten blocks

* *BLOCK_RD* - number of the received blocks

* *BLOCK_OK* - number of the blocks with correct data

* *BLOCK_ERR* - number of the blocks with errors

* *SPD_CURR* - speed of data transfer during of last 4 second  [Mbytes per second]

* *SPD_AVR*  - speed of data transfer with program start [Mbytes per second]

* *STATUS*   - content of STATUS register

* *SIG*      - value of SIG register

* *TIME*     - current time of test

Press Ctrl-C for exit;

Result of test:

<pre>

Cancel

 TRD :   0     245490     245489     245489          0      799.8      799.8     0x0309  0xAAAAAAAA  5:06 

Result of receiving data 

 Recieved blocks :   245490 

 Correct blocks  :   245489 

 Incorrect blocks:   0 

 Total errors    :   0 

 Speed           :   799.8 [Mbytes/s] 

 Time of test    :   5 min 07 sec

All data is correct. No error

</pre>

799.8 - PCI Express v1.1 x4 - project AMBPEX5_v20_SX50T_WISHBONE