Simulation

Version 1 (Dmitry Smekhov, 09/12/2015 11:41 pm)

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h1. Simulation
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h2. List of tests for ADM projects
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|_. Number|_. Name |_. Description |
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|_. 0 | test_dsc_incorrect | DMA with incorrect block of descriptos.  DMA must be stopped |
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|_. 1 | test_read_4kb | Receive one block of 4 kB |
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|_. 2 | test_adm_read_8kb | Receive two blocks of 4 кB. There are two descriptor in one block of descriptors  |
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|_. 3 | test_adm_read_16kb| Receive for blocks of 4 kB. There are two blocks of descriptors |
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|_. 4 | test_adm_write_16kb | Transmit for blocks of 4 kB.  There are two blocks of descriptors |
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|_. 5 | test_block_main | Check access to block PE_MAIN |
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h2. List of tests for WISHBONE projects
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|_. Number|_. Name |_. Description |
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|_. 0 | test_dsc_incorrect | DMA with incorrect block of descriptos.  DMA must be stopped  |
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|_. 1 | test_read_4kb | Receive one block of 4 kB  |
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|_. 2 | test_read_8kb | Receive two blocks of 4 кB. There are two descriptor in one block of descriptors  |
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|_. 3 | test_read_reg | Check access to registers |
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h2. Start test with script
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The projects ac701_a200t_core and sp605_lx45t_wishbone have script *src\testbench\ahdl\run_ahdl.tcl*; Script start all tests; Script save console log for each test; Example of console log in the dir *src\testbench\ahdl\log_example*; 
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Script create file *global_tc_summary.log* with results from all tests;
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Example of *global_tc_summary.log*
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<pre><code>Global AC701_A200T_CORE TC log:
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test_dsc_incorrect PASSED
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test_read_4kB PASSED
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test_adm_read_8kb PASSED
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test_adm_read_16kb PASSED
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</code></pre>