DS_DMA¶

Objective¶

Development PCI Express IP Core for  Virtex 5, Virtex 6, Spartan 6 FPGA.

Russian version

Main features¶

• PCI Express 1.1 x1,x4,x8 or 2.0 x4
• two address space: BAR0, BAR1
• access to registers can only be single 32-bit instructions
• local bus: 64 bit, 266 MHz
• two independent bidirectional DMA channel
• DMA channel only works in the SCATTER-GATHER mode
• The minimum unit of data for channel DMA - 4 kB
• Descriptors combined into the block descriptors. The maximum number of descriptors in the block - 63
• DMA channel uses 40 bit addresses

Description¶

• Struct
• The control registers
• Algorithms for main operations

IP Core¶

• pcie_core64_m1 - PCI Express v1.1 x8, Virtex 5, local bus 64 bit
• pcie_core64_m4 - PCI Express v2.0 x4, Virtex 6, local bus 64 bit
• pcie_core64_m6 - PCI Express v1.1 x1, Spartan 6, local bus 64 bit

Project¶

ADM

• ambpex5_v20_sx50t_core - pcie_core64_m1 on AMBPEX5 (Virtex 5)
• ml605_lx240t_core - pcie_core64_m4 on ML605 (Virtex 6)
• sp605_lx45t_core - pcie_core64_m6 on SP605 (Spartan 6)

Wishbone

• sp605_lx45t_wishbone - pcie_core64_m6 on SP605 (Spartan 6)

Software¶

• Linux
• Windows

The speed of data transfer¶

• ambpex5_v20_sx50t_core
• ml605_lx240t_core
• sp605_lx45t_core

Access to source code¶

Access to the source code is available via Subversion: http://svn.1gb.ru/ds-dma
login: guest
password: guest

Access to automated documentation¶

• ambpex5_v20_sx50t_core - http://src.ds-dev.ru/projects/ds_dma/ambpex5_v20_sx50t_core/classambpex5__v20__sx50t__core.html

• pcie_core64_m1 - http://src.ds-dev.ru/projects/ds_dma/core/classpcie__core64__m2.html

Additionally¶

• FAQ

• Publications

• Links

• The structure of the repository