English
Version 1 (Dmitry Smekhov, 02/24/2012 11:31 pm)
| 1 | 1 | h1. DS_DMA |
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| 2 | 1 | ||
| 3 | 1 | h2. Objective |
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| 4 | 1 | ||
| 5 | 1 | Development PCI Express IP Core for Virtex 5, Virtex 6, Spartan 6 FPGA. |
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| 6 | 1 | ||
| 7 | 1 | [[ds-dma:|Russian version]] |
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| 8 | 1 | ||
| 9 | 1 | h2. Main features |
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| 10 | 1 | ||
| 11 | 1 | * PCI Express 1.1 x1,x4,x8 or 2.0 x4 |
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| 12 | 1 | * two address space: BAR0, BAR1 |
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| 13 | 1 | * access to registers can only be single 32-bit instructions |
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| 14 | 1 | * local bus: 64 bit, 266 MHz |
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| 15 | 1 | * two independent bidirectional DMA channel |
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| 16 | 1 | * DMA channel only works in the SCATTER-GATHER mode |
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| 17 | 1 | * The minimum unit of data for channel DMA - 4 kB |
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| 18 | 1 | * Descriptors combined into the block descriptors. The maximum number of descriptors in the block - 63 |
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| 19 | 1 | * DMA channel uses 40 bit addresses |
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| 20 | 1 | ||
| 21 | 1 | h2. Description |
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| 22 | 1 | ||
| 23 | 1 | * [[Struct]] |
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| 24 | 1 | * [[The control registers]] |
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| 25 | 1 | * [[Algorithms for main operations]] |
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| 26 | 1 | ||
| 27 | 1 | ||
| 28 | 1 | h2. IP Core |
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| 29 | 1 | ||
| 30 | 1 | * [[pcie_core64_m1_en|pcie_core64_m1]] - PCI Express v1.1 x8, Virtex 5, local bus 64 bit |
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| 31 | 1 | * [[pcie_core64_m4_en|pcie_core64_m4]] - PCI Express v2.0 x4, Virtex 6, local bus 64 bit |
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| 32 | 1 | * [[pcie_core64_m6_en|pcie_core64_m6]] - PCI Express v1.1 x1, Spartan 6, local bus 64 bit |
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| 33 | 1 | ||
| 34 | 1 | h2. Project |
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| 35 | 1 | ||
| 36 | 1 | h3. ADM |
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| 37 | 1 | * [[ambpex5_v20_sx50t_core_en|ambpex5_v20_sx50t_core]] - pcie_core64_m1 on AMBPEX5 (Virtex 5) |
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| 38 | 1 | * [[ml605_lx240t_core_en|ml605_lx240t_core]] - pcie_core64_m4 on ML605 (Virtex 6) |
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| 39 | 1 | * [[sp605_lx45t_core_en|sp605_lx45t_core]] - pcie_core64_m6 on SP605 (Spartan 6) |
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| 40 | 1 | ||
| 41 | 1 | h3. Wishbone |
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| 42 | 1 | * [[sp605_lx45t_wishbone_en|sp605_lx45t_wishbone]] - pcie_core64_m6 on SP605 (Spartan 6) |
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| 43 | 1 | ||
| 44 | 1 | ||
| 45 | 1 | h2. Sowtware |
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| 46 | 1 | ||
| 47 | 1 | * [[Linux_en|Linux]] |
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| 48 | 1 | * [[Windows_en|Windows]] |
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| 49 | 1 | ||
| 50 | 1 | h2. The speed of data transfer |
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| 51 | 1 | ||
| 52 | 1 | * [[ambpex5_v20_sx50t_core_res_en|ambpex5_v20_sx50t_core]] |
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| 53 | 1 | * [[ml605_lx240t_core_res_en|ml605_lx240t_core]] |
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| 54 | 1 | * [[sp605_lx45t_core_res_en|sp605_lx45t_core]] |
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| 55 | 1 | ||
| 56 | 1 | h2. Access to source code |
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| 57 | 1 | ||
| 58 | 1 | Access to the source code is available via Subversion: http://svn.1gb.ru/ds-dma |
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| 59 | 1 | login: guest |
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| 60 | 1 | password: guest |
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| 61 | 1 | ||
| 62 | 1 | h2. Access to automated documentation |
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| 63 | 1 | ||
| 64 | 1 | * *ambpex5_v20_sx50t_core* - http://src.ds-dev.ru/projects/ds_dma/ambpex5_v20_sx50t_core/classambpex5__v20__sx50t__core.html |
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| 65 | 1 | ||
| 66 | 1 | * *pcie_core64_m1* - http://src.ds-dev.ru/projects/ds_dma/core/classpcie__core64__m2.html |
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| 67 | 1 | ||
| 68 | 1 | h2. Additionally |
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| 69 | 1 | ||
| 70 | 1 | * [[FAQ_en|FAQ]] |
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| 71 | 1 | ||
| 72 | 1 | * [[Publications]] |
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| 73 | 1 | ||
| 74 | 1 | * [[Links]] |
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| 75 | 1 | ||
| 76 | 1 | * [[The structure of the repository]] |